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| 1 isl28107, isl28207, isl28407 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. precision single, dual and quad low noise operational amplifiers isl28107, isl28207, isl28407 the isl28107, isl28207 and isl28407 are single, dual and quad amplifiers featuring low noise, low input bias current, and low offset and temperature drift. this makes them the ideal choice for applications requiring both high dc accuracy and ac performance. the combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls, and industrial controls. the isl28107 is available in an 8 ld soic, msop and tdfn package. the isl28207 is available in the 8 ld soic and msop packages. th e isl28407 will be offered in an 14 ld soic, tssop and 16 ld qfn packages. all devices are offered in standard pin configurations and operate over the extended temperature range to -40c to +125c. applications* (see page 26) ? precision instruments ? medical instrumentation ? spectral analysis equipment ? active filter blocks ? microphone pre-amplifier ? thermocouples and rtd reference buffers ? data acquisition ? power supply control features ? low input offset . . . . . . . . . . . . . . . . 75v, max. ? input bias current . . . . . . . . . . . . . . . . . . . .15pa ? superb temperature drift - voltage offset . . . . . . . . . . . . . 0.65v/c, max. - input current . . . . . . . . . . . . . . . 0.9pa/c, max ? outstanding esd performance - human body model . . . . . . . . . . . . . . . . . 4.5kv - machine model . . . . . . . . . . . . . . . . . . . . .500v - charged device model . . . . . . . . . . . . . . . 1.5kv ? very low voltage noise, 10hz . . . . . . . . 14nv/ hz ? low current consumption (per amp) . . . . 0.29ma, max. ? gain-bandwidth product . . . . . . . . . . . . . . . 1mhz ? wide supply range. . . . . . . . . . . . . . . 4.5v to 40v ? operating temperature range . . . -40c to +125c ? no phase reversal ? pb-free (rohs compliant) related literature* (see page 26) ?see an1508 ?isl281x7soiceval1z evaluation board user?s guide? ?see an1509 ?isl282x7soiceval2z evaluation board user?s guide? typical application input noise voltage spectral density - + output v+ r 1 v- r 2 c1 c2 sallen-key low pass filter (1khz) v in 19.1k 48.7k 3.3nf 8.2nf frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 0.1 1 10 100 1k 10k 100k v + = 19v a v = 1 september 9, 2010 fn6631.3
2 fn6631.3 september 9, 2010 ordering information part number (notes 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl28107fbz 28107 fbz -40 to +125 8 ld soic m8.15e isl28107fbz-t7 (note 1) 28107 fbz -40 to +125 8 ld soic m8.15e isl28107fbz-t13 (note 1) 28107 fbz -40 to +125 8 ld soic m8.15e isl28107fbz-t7a (note 1) 28107 fbz -40 to +125 8 ld soic m8.15e isl28107fuz 8107z -40 to +125 8 ld msop m8.118 isl28107fuz-t7 (note 1) 8107z -40 to +125 8 ld msop m8.118 isl28107fuz-t13 (note 1) 8107z -40 to +125 8 ld msop m8.118 isl28107fuz-t7a (note 1) 8107z -40 to +125 8 ld msop m8.118 isl28107frtz 107z -40 to +125 8 ld tdfn l8.3x3a isl28107frtz-t7 (note 1) 107z -40 to +125 8 ld tdfn l8.3x3a ISL28107FRTZ-T13 (note 1) 107z -40 to +125 8 ld tdfn l8.3x3a isl28107frtz-t7a (note 1) 107z -40 to +125 8 ld tdfn l8.3x3a isl28207fbz 28207 fbz -40 to +125 8 ld soic m8.15e isl28207fbz-t7 (note 1) 28207 fbz -40 to +125 8 ld soic m8.15e isl28207fbz-t13 (note 1) 28207 fbz -40 to +125 8 ld soic m8.15e isl28207fbz-t7a (note 1) 28207 fbz -40 to +125 8 ld soic m8.15e isl28207frtz 207z -40 to +125 8 ld tdfn l8.3x3a isl28207frtz-t7 (note 1) 207z -40 to +125 8 ld tdfn l8.3x3a isl28207frtz-t13 (note 1) 207z -40 to +125 8 ld tdfn l8.3x3a isl28207frtz-t7a (note 1) 207z -40 to +125 8 ld tdfn l8.3x3a coming soon isl28407fbz 28407 -40 to +125 14 ld soic m14.15 coming soon isl28407fbz-t7a (note 1) 28407 -40 to +125 14 ld soic m14.15 coming soon isl28407fvz (note 1) 28407 -40 to +125 14 ld tssop m14.173 coming soon isl28407fvz-t13 (note 1) 28407 -40 to +125 14 ld tssop m14.173 coming soon isl28407fvz-t7a (note 1) 28407 -40 to +125 14 ld tssop m14.173 coming soon isl28407frz 28407 -40 to +125 16 ld qfn l16.4x4 coming soon isl28407frz-t13 (note 1) 28407 -40 to +125 16 ld qfn l16.4x4 coming soon isl28407frz-t7a (note 1) 28407 -40 to +125 16 ld qfn l16.4x4 isl28107soiceval1z evaluation board isl28207soiceval2z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page fo r isl28107 , isl28207 and isl28407 . for more information on msl pl ease see techbrief tb363 . isl28107, isl28207, isl28407 3 fn6631.3 september 9, 2010 pin configurations isl28107 (8 ld soic, msop) top view isl28107 (8 ld tdfn) top view isl28207 (8 ld soic) top view isl28207 (8 ld tdfn) top view isl28407 (14 ld soic, tssop) top view isl28407 (16 ld qfn) top view nc -in +in v - 1 2 3 4 8 7 6 5 nc v+ v out nc + - 2 3 4 1 7 6 5 8 nc -in +in v- nc v+ v out nc + - v out a -in_a +in_a v - 1 2 3 4 8 7 6 5 v+ v out b -in_b +in_b + - +- 2 3 4 1 7 6 5 8 v out _a -in_a +in_a v- v+ v out _b -in_b +in_b + - +- -+ - + -+ - + bc ad v out _ a -in _ a +in _ a v + 1 2 3 4 5 6 7 10 9 8 11 12 13 14 +in _ b -in _ b v out _ b v - +in _ c -in _ c v out _ c v out _ d -in _ d +in _ d -+ a - + d -+ b - + c +in _ d -in _ a +in _ a v + +in _ b -in _ b v out _ b -in _ c v out _ c v - +in _ c v out _ a v out _ d nc nc 1 2 3 4 5 678 12 11 10 9 13 14 15 16 -in _ d isl28107, isl28207, isl28407 4 fn6631.3 september 9, 2010 pin descriptions isl28107 (8 ld soic, msop, tdfn) isl28207 (8 ld soic, tdfn) isl28407 (14 ld soic, tssop) isl28407 (16 ld qfn) pin name equivalent circuit description 3 - - - +in circuit 1 amplifier non-inverting input -3 3 2+in_a -5 5 4+in_b - - 10 9 +in_c --1211+in_d 441110v-circuit 3neg ative power supply 2 - - - -in circuit 1 amplifier inverting input -2 2 1-in_a -6 6 5-in_b -- 9 8-in_c --1312-in_d 7 8 4 3 v+ circuit 3 positive power supply 6- - -v out circuit 2 amplifier output -1 1 15v out _a -7 7 6v out _b -- 8 7v out _c --1414v out _d 1, 5, 8 - - 13, 16 nc - no internal connection pd pd - pd pd - thermal pad - tdfn and qfn packages only. connect thermal pad to ground or most negative potential. v+ v- out circuit 2 circuit 1 v+ v- circuit 3 in- v+ v- in+ capacitively triggered 500 500 isl28107, isl28207, isl28407 5 fn6631.3 september 9, 2010 table of contents absolute maximum ratings ....................................................................................................... ......... 6 thermal information ............................................................................................................ .............. 6 operating conditions ........................................................................................................... ............... 6 electrical specifications. ..................................................................................................... ................ 6 electrical specifications ...................................................................................................... ................ 8 typical performance curves ..................................................................................................... ........ .10 applications information ....................................................................................................... ............ 19 functional description......................................................................................................... ............. 19 operating voltage range........................................................................................................ .......... 19 input esd diode protection ..................................................................................................... ......... 19 output current limiting ........................................................................................................ ........... 19 output phase reversal.......................................................................................................... ........... 19 using only one channel......................................................................................................... .......... 19 power dissipation.............................................................................................................. .............. 19 isl28107, isl28207, isl28407 spice model ...................................................................................... 20 license statement.............................................................................................................. ............. 20 characterization vs simulation results......................................................................................... ..... 23 revision history ............................................................................................................... ................. 25 products ....................................................................................................................... ..................... 26 package outline drawing ....................................................................................................... .......... 27 package outline drawing ....................................................................................................... .......... 28 package outline drawing ....................................................................................................... .......... 29 package outline drawing ........................................................................................................ ......... 30 package outline drawing ....................................................................................................... .......... 31 package outline drawing ....................................................................................................... .......... 32 isl28107, isl28207, isl28407 6 fn6631.3 september 9, 2010 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . 42v maximum differential input current . . . . . . . . . . . . . 20ma maximum differential input voltage . . . (v-) - 0.5v to (v+) + 0.5v min/max input voltage . . . . . . . . (v-) - 0.5v to (v+) + 0.5v max/min input current for input voltage >v+ or 8 fn6631.3 september 9, 2010 t s settling time to 0.1% 10v step; 10% to v out a v = -1 v out = 10v p-p , r g = r f =10k, r l =2k to v cm 29 s settling time to 0.01% 10v step; 10% to v out a v = -1, v out = 10v p-p , r g = r f =10k, r l =2k to v cm 31.2 s t ol output overload recovery time a v = 100, v in = 0.2v, r l = 2k to v cm 6s electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . (continued) parameter description conditions min (note 8) typ max (note 8) unit electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . parameter description conditions min (note 8) typ max (note 8) unit v os offset voltage magnitude; soic package -75 5 75 v -140 140 v offset voltage magnitude; msop package -100 5 100 v -180 180 v offset voltage magnitude; tdfn package isl28107 -100 10 100 v -190 190 v isl28207 -100 10 100 v -175 175 v tcv os offset voltage drift; soic package -0.65 0.1 0.65 v/c offset voltage drift; msop package -0.85 0.1 0.85 v/c offset voltage drift; tdfn package isl28107 -0.9 0.1 0.9 v/c isl28207 -0.75 0.1 0.75 v/c i b input bias current t a = -40c to +85c -300 15 300 pa t a = -40c to +125c -600 600 pa tci b input bias current drift t a = -40c to +85c -0.9 0.19 0.9 pa/c t a = -40c to +125c -3.5 0.26 3.5 pa/c i os input offset current t a = -40c to +85c -300 15 300 pa t a = -40c to +125c -600 600 pa tci os input offset current drift t a = -40c to +85c -0.9 0.19 0.9 pa/c t a = -40c to +125c -3.5 0.26 3.5 pa/c v cm common mode input voltage range guaranteed by cmrr test -3 3 v cmrr common-mode rejection ratio v cm = -3v to +3v 115 145 db psrr power supply rejection ratio v s = 2.25v to 5v 115 145 db a vol open-loop gain v o = -3v to +3v, r l = 10k to ground 3,000 40,000 v/mv isl28107, isl28207, isl28407 9 fn6631.3 september 9, 2010 v oh output voltage high r l = 10k to ground 3.5 3.7 v 3.2 v r l = 2k to ground 3.3 3.55 v 3.1 v v ol output voltage low r l = 10k to ground -3.7 -3.5 v -3.2 v r l = 2k to ground -3.55 -3.3 v -3.1 v i s supply current/amplifier r l = open 0.21 0.29 ma 0.35 ma i sc output short-circuit current (note 9) 40 ma ac specifications gbw gain bandwidth product 1 mhz thd + n total harmonic distortion + noise 1khz, g = 1, v o = 2.5v rms , r l = 2k 0.0053 % transient response sr slew rate a v = 10, r l = 2k 0.32 v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 355 ns fall time 90% to 10% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 370 ns t s settling time to 0.1% 4v step; 10% to v out a v = -1, v out = 4v p-p , r f = r g = 2k , r l =2k to v cm 12.4 s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r f = r g = 2k , r l =2k to v cm 22 s notes: 8. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. 9. output short circuit current is the minimum current (source or sink) when the output is driven into the supply rails with r l =0 to ground. electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . (continued) parameter description conditions min (note 8) typ max (note 8) unit isl28107, isl28207, isl28407 10 fn6631.3 september 9, 2010 typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. figure 1. input offset voltage vs temperature, v s = 15v figure 2. input offset voltage vs temperature, v s = 5v figure 3. input offset voltage distribution, v s = 15v figure 4. input offset voltage distribution, v s = 5v figure 5. tcv os vs number of amplifiers, v s =15v figure 6. tcv os vs number of amplifiers, v s =5v temperature (c) v os (v) v s = 15v -30 -20 -10 0 10 20 30 -50 0 50 100 150 temperature (c) v os (v) v s = 5v -30 -20 -10 0 10 20 30 -50 0 50 100 150 v s = 15v 0 200 400 600 800 1000 1200 1400 -100-80-60-40-20 0 20406080100 v os (v) number of amplifiers v s = 5v 0 200 400 600 800 1000 1200 1400 -100 -80 -60 -40 -20 0 20 40 60 80 100 v os (v) number of amplifiers number of amplifiers v s = 15v 0 2 4 6 8 10 12 14 16 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 tcv os (v/c) number of amplifiers v s = 5v 0 2 4 6 8 10 12 14 16 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 tcv os (v/c) isl28107, isl28207, isl28407 11 fn6631.3 september 9, 2010 figure 7. positive bias current vs temperature, v s = 15v figure 8. positive bias current vs temperature, v s = 5v figure 9. tc ib+ vs number of amplifiers, v s =15v figure 10. tc ib+ vs number of amplifiers, v s =5v figure 11. negative bias current vs temperature, v s = 15v figure 12. negative bias current vs temperature, v s = 5v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) temperature (c) ib+ (pa) v s = 15v -200 -100 0 100 200 -50 -25 0 25 50 75 100 125 150 temperature (c) ib+ (pa) v s = 5v -200 -100 0 100 200 -50 -25 0 25 50 75 100 125 150 v s = 15v 0 10 20 30 40 50 60 70 80 -1.8 -1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 tc ib+ (pa/c) number of amplifiers v s = 5v 0 10 20 30 40 50 60 70 80 -1.8 -1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 tc ib+ (pa/c) number of amplifiers temperature (c) ib- (pa) v s = 15v -200 -100 0 100 200 -50 -25 0 25 50 75 100 125 150 temperature (c) ib- (pa) vs = 5v -200 -100 0 100 200 -50 -25 0 25 50 75 100 125 150 isl28107, isl28207, isl28407 12 fn6631.3 september 9, 2010 figure 13. tc ib- vs number of amplifiers, v s =5v figure 14. tc ib- vs number of amplifiers, v s =15v figure 15. offset current vs temperature, v s = 15v figure 16. offset current vs temperature, v s =5v figure 17. tci os - vs number of amplifiers, v s =15v figure 18. tci os - vs number of amplifiers, v s =5v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) v s = 5v 0 10 20 30 40 50 60 70 80 90 100 -1.8 -1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 tc ib- (pa/c) number of amplifiers v s = 15v 0 10 20 30 40 50 60 70 80 -1.8 -1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 tc ib- (pa/c) number of amplifiers v s = 15v -200 -150 -100 -50 0 50 100 150 200 -50 0 50 100 150 temperature (c) i os (pa) v s = 5v -200 -150 -100 -50 0 50 100 150 200 -50 0 50 100 150 temperature (c) i os (pa) v s = 15v 0 5 10 15 20 25 30 35 40 45 50 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 tci os (pa/c) number of amplifiers v s = 5v 0 5 10 15 20 25 30 35 40 45 50 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 tci os (pa/c) number of amplifiers isl28107, isl28207, isl28407 13 fn6631.3 september 9, 2010 figure 19. cmrr vs temperature figure 20. psrr vs temperature figure 21. a vol vs temperature figure 22. v oh vs temperature, v s = 15v, r l =10k figure 23. v ol vs temperature, vs = 15v, r l =10k figure 24. v oh vs temperature, v s = 15v, r l =2k typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) 120 140 160 180 -50 0 50 100 150 temperature (c) cmrr (db) v cm = 13v 100 120 140 160 180 -50 0 50 100 150 temperature (c) psrr (db) v s = 2.25v to 20v 3000 13000 23000 33000 43000 53000 63000 -50 0 50 100 150 temperature (c) a vol (v/mv) v o = 13v 13.2 13.4 13.6 13.8 14.0 14.2 14.4 -50 0 50 100 150 temperature (c) v oh (v) vs = 15v r l = 10k -14.4 -14.2 -14.0 -13.8 -13.6 -13.4 -13.2 -50 0 50 100 150 temperature (c) v ol (v) v s = 15v r l = 10k 13.2 13.4 13.6 13.8 14.0 14.2 14.4 -50 0 50 100 150 temperature (c) v oh (v) v s = 15v r l = 2k isl28107, isl28207, isl28407 14 fn6631.3 september 9, 2010 figure 25. v ol vs temperature, v s = 15v, r l =2k figure 26. v oh vs temperature, v s = 5v, r l =10k figure 27. v ol vs temperature, v s = 5v, r l =10k figure 28. supply current vs temperature figure 29. positive short circuit current vs temperature figure 30. negative short circuit current vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) -14.4 -14.2 -14.0 -13.8 -13.6 -13.4 -13.2 -50 0 50 100 150 temperature (c) v ol (v) v s = 15v r l = 2k 3.2 3.4 3.6 3.8 4.0 4.2 4.4 -50 0 50 100 150 temperature (c) v oh (v) v s = 5v r l = 10k -4.4 -4.2 -4.0 -3.8 -3.6 -3.4 -3.2 -50 0 50 100 150 temperature (c) v ol (v) v s = 5v r l = 10k 15v 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 0 50 100 150 temperature (c) i s (ma) 2.25v 20 25 30 35 40 45 50 55 60 -50 0 50 100 150 temperature (c) i sc+ (ma) i sc+ @ 15v 20 25 30 35 40 45 50 55 60 -50 0 50 100 150 temperature (c) i sc- (ma) i sc- @ 15v isl28107, isl28207, isl28407 15 fn6631.3 september 9, 2010 figure 31. input noise voltage 0.1hz to 10hz figure 32. input noise voltage spectral density figure 33. input noise current spectral density figure 34. psrr vs frequency, v s = 5v, 15v figure 35. cmrr vs frequency, v s = 2.25, 5v, 15v figure 36. input offset voltage vs input common mode voltage, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) time (s) input noise voltage (nv) 012345678910 -200 -150 -100 -50 0 50 100 150 200 v + = 19v r l = inf, r g = 10, r f = 100k a v = 10,000 c l = 4pf frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 0.1 1 10 100 1k 10k 100k v + = 19v a v = 1 v + = 19v a v = 1 frequency (hz) 0.1 1 input noise current (pa/ hz) 0.1 1 10 100 1k 10k 100k 0.01 psrr (db) 100 1k 10k 100k 1m frequency (hz) 10 -20 0 20 40 60 80 100 r l = inf a v = +1 v source = 1v p-p c l = 4pf psrr+ v s = 5v , v s = 15v psrr- v s = 5v , v s = 15v cmrr (db) 100 1k 10k 100k 1m frequency (hz) 10 0 20 40 60 80 100 120 140 160 100m 10m 1 0.1 r l = inf a v = +1 v cm = 1v p-p c l = 4pf v s = 2.25v, 5v , 15v v os (v) input common mode voltage -60 -40 -20 0 20 40 60 -15 -10 -5 0 5 10 15 +25c +125c -40c isl28107, isl28207, isl28407 16 fn6631.3 september 9, 2010 figure 37. open-loop gain, phase vs frequency, r l = 10k , c l = 10pf figure 38. open-loop gain, phase vs frequency, r l = 10k , c l = 100pf figure 39. frequency resp onse vs closed loop gain figure 40. frequency response vs feedback resistance r f /r g figure 41. gain vs frequency vs r l figure 42. gain vs frequency vs r l typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) open loop gain (db)/phase ( ) frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 10pf gain phase open loop gain (db)/phase ( ) frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 100pf gain phase frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 -20 -10 0 10 20 30 40 50 60 70 a v = 1 a v = 100 a v = 1000 v + = 20v v out = 100mv p-p c l = 4pf r l = 10k a v = 10 r g = 1k, r f = 100k r g = 100, r f = 100k r g = open, r f = 0 r g = 10k, r f = 100k normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -12 -10 -8 -6 -4 -2 0 2 4 6 8 r f = r g = 100 r f = r g = 10k r f = r g = 1k v + = 5v r l = 10k a v = +2 v out = 10mv p-p c l = 4pf r f = r g = 100k normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 v + = 5v a v = +1 v out = 10mv p-p c l = 4pf r l = 1k r l = 499 r l = 10k r l = 100k normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 v + = 20v a v = +1 v out = 100mv p-p c l = 4pf r l = 10k r l = 100k r l = 1k r l = 499 isl28107, isl28207, isl28407 17 fn6631.3 september 9, 2010 figure 43. gain vs frequency vs c l figure 44. gain vs frequency vs output voltage figure 45. gain vs frequency vs supply voltage figure 46. crosstalk vs frequency, v s = 5v, 15v figure 47. large signal 10v step response, v s = 15v figure 48. large signal transient response vs r l v s = 5v, 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -8 -6 -4 -2 0 2 4 6 8 v s = 15v r l = 10k a v = +1 v out = 100mv p-p c l = 334pf c l = 104pf c l = 224pf c l = 51pf c l = 4pf frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k - -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 v s = 5v a v = +1 r l = inf c l = 4pf v out = 1v p-p v out = 500mv p-p v out = 200mv p-p v out = 100mv p-p v out = 10mv p-p v out = 50mv p-p normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -16 -14 -12 -10 -8 -6 -4 -2 0 2 c l = 4pf r l = 10k a v = +1 v out = 100mv p-p v s = 20v v s = 2.25v v s = 5v v s = 15v 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m 10m crosstalk (db) frequency (hz) r l = 10k a v = +1 v out = 1v p-p c l = 4pf v s = 5v v s = 15v -6 -4 -2 0 2 4 6 0 50 100 150 200 250 300 350 400 time (s) large signal (v) v + = 15v a v = 11 c l = 4pf v out = 10v p-p r f = 10k, r g = 1k r l = 10k r l = 2k 0 5 10 15 20 25 30 time (s) large signal (v) -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 a v = 1 c l = 4pf v out = 4v p-p 35 v s = 5v , 15v , r l = 10k v s = 5v , 15v , r l = 2k isl28107, isl28207, isl28407 18 fn6631.3 september 9, 2010 figure 49. small signal transient response v s = 5v, 15v, 20v figure 50. positive output overload response time, v s = 15v figure 51. negative output overload response time, v s = 15v figure 52. % overshoot vs load capacitance, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c unless otherwise specified. (continued) time (s) small signal (v) -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0 5 10 15 20 25 30 35 40 r l = 2k, 10k a v = 1 c l = 4pf v out = 100mv p-p v s = 5v , 15v, 20v time (s) output (v) input (v) -0.06 -0.02 0.02 0.06 0.10 0.14 0.18 0.22 0.26 0 20 40 60 80 100 120 140 160 180 200 -1 1 3 5 7 9 11 13 15 input output v s = 15v r l = 10k a v = 100 c l = 4pf r f = 10k, r g = 100 v in = 200mv p-p time (s) output (v) input (v) -0.26 -0.22 -0.18 -0.14 -0.10 -0.06 -0.02 0.02 0.06 0 20 40 60 80 100 120 140 160 180 200 -15 -13 -11 -9 -7 -5 -3 -1 1 input output v s = 15v r l = 10k a v = 100 c l = 4pf r f = 10k, r g = 100 v in = 200mv p-p capacitance (pf) overshoot (%) 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1,000 10,000 o v e r s h o o t - v s = 15v r l = 10k a v = 1 v out = 100mv p-p o v e r s h o o t + isl28107, isl28207, isl28407 19 fn6631.3 september 9, 2010 applications information functional description the isl28107, isl28207 and isl28407 are single, dual and quad, very low 1/f noise (14nv/ hz @ 10hz) precision op-amps. these amplifiers feature very high open loop gain (50kv/mv) for excellent cmrr (145db), and gain accuracy. both devices are fabricated in a new precision 40v complementary bipolar di process. the super-beta npn input stage with bias current cancellation prov ides bipolar-like levels of ac performance with the low input bias currents approaching jfet levels. the temperature stabilization provided by bias current ca ncellation removes the high input bias current temperature coefficient commonly found in jfet amplifiers. fi gures 7 and 8 show the input bias current variation over temperature. the input offset voltage (v os ) has an very low, worst case value of 75v max at +25c and a maximum t c of 0.65v/c. figure 36 shows v os as a function of supply voltage and temperature with the common mode voltage at 0v for split supply operation. the complimentary bipolar output stage maintains stability driving large capacitive loads (to 10nf) without external compensation. the small signal overshoot vs. load capacitance is shown in figure 52. operating voltage range the devices are designed to operate over the 4.5v (2.25v) to 40v (20v) range and are fully characterized at 10v (5v) and 30v (15v). both dc and ac performance remain vi rtually unchanged over the complete 4.5v to 40v operating voltage range. parameter variation with operating voltage is shown in the ?typical performance curves? beginning on page 10. the input common mode voltage range sensitivity to temperature is shown in figure 36 (15v). input esd diode protection the input terminals (in+ and in-) each have internal esd protection diodes to the positive and negative supply rails, a series connected 500 current limiting resistor followed by an anti-parallel diode pair across the input npn transistors (circuit 1 in ?pin descriptions? on page 4). the resistor-esd diode configuration enables a wide differential input voltage range equal to the lesser of the maximum supply voltage in the ?absolute maximum ratings? on page 6 (42v) or, a maximum of 0.5v beyond the v+ and v- supply voltage. the internal protection resistors eliminate the need for external input current limiting resistors in unity gain connections and other circuit applications where large voltages or high slew rate signals are present. al though the amplifier is fully protected, high input slew rates that exceed the amplifier slew rate (0.32v/s) may cause output distortion. output current limiting the output current is internally limited to approximately 40ma at +25c and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. this applies to only 1 amplifier at a time for the dual op-amp. continuous operation under these conditions may degrade long term reliability. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl28107, isl28207 and isl28407 are immune to output phase reversal, even when the input voltage is 1v beyond the supplies. using only one channel the isl28207 is a dual op-amp. if the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. the unused channel will oscillate if the input and output pins are floating. this will result in higher than expected supply currents and possible noise injection into the channel being used. the proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input (as shown in figure 53). power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage figure 53. preventing oscillations in unused channels - + t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2) isl28107, isl28207, isl28407 20 fn6631.3 september 9, 2010 ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28107, isl28207, isl28407 spice model figure 54 shows the spice model schematic and figure 55 shows the net list for the isl28107, isl28207 and isl28407 spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac para meters incorporated into the model are: 1/f and flatband noise, slew rate, cmrr, gain and phase. the dc parameters are vos, ios, total supply current and output voltage swing. the model uses typical parameters given in the ?electrical specifications? table beginnin g on page 6. the avol is adjusted for 155db with the dominate pole at 0.01hz. the cmrr is set (145db, f cm = 100hz). the input stage models the actual device to present an accurate ac representation. the model is configured for ambient temperature of +25c. figures 56 through 66 show the characterization vs simulation results for the noise voltage, closed loop gain vs frequency, closed loop gain vs rl, large signal step response, open loop gain phase and simulated cmrr vs frequency. license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-model without prior notice. isl28107, isl28207, isl28407 21 fn6631.3 september 9, 2010 figure 54. spice schematic v in - v out v+ v- + - + - + - + - + - d12 r17 600 ios 15pa r1 5e11 r2 5e11 dn 0.1v v5 in+ vin- vcm superb q1 q2 superb cascode cascode q4 q5 r3 4.45k r4 4.45k iee1 96e-6 d1 dx mirror q3 iee 200e-6 1 2 3 4 5 6 v++ + - + - v in + 24 25 4 5 v++ vc vmid v-- vcm + - vos 5e-6 + - + - d2 dx d3 dx v1 1.86v v2 1.86v g1 g2 r5 1 r6 1 4 5 v++ 11 12 10 + - + - + - + - d4 dx d5 dx v3 1.86v v4 1.86v g3 g4 r7 2.55e10 r8 vg 14 13 c2 6.25pf c3 r9 1 r10 1 6.25pf 2.55e10 vmid vmid + - + - g5 g6 r11 1 r12 18 17 l1 1.59e-3 l2 1.59e-3 1 vcm eos + - + - isy 0.21ma v++ v- v+ + - + - g7 g8 r15 90 r16 22 23 90 v-- vcm vc + - + - d10 dy d11 dy d8 dx d9 dx d6 dx d7 dx vg v++ v-- v-- + - + - v5 v6 1.12v 1.12v vg + - + - vc g10 g9 vout 20 21 8 9 7 en voltage noise input stage 1 st gain stage mid supply ref 2 nd gain stage common mode gain stage supply isolation stage e2 e3 output stage c6 1.2pf c4 2pf c5 2pf isl28107, isl28207, isl28407 22 fn6631.3 september 9, 2010 * source isl28107_spicemodel * revision a, october 28th 2009 lafontaine * model for noise, supply currents, 145db f=100hz cmrr, *155db f=0.01hz aol *copyright 2009 by intersil corporation *refer to data sheet ?license statement? use of *this model indicates your acceptance with the *terms and provisions in the license statement. * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28107subckt vin+ vin-v+ v- vout * source isl28127_spicemodel_0_0 * *voltage noise e_en in+ vin+ 25 0 1 r_r17 25 0 600 d_d12 24 25 dn v_v7 24 0 0.1 * *input stage i_ios in+ vin- dc 15e-12 c_c6 in+ vin- 1.2e-12 r_r1 vcm vin- 5e11 r_r2 in+ vcm 5e11 q_q1 2 vin- 1 superb q_q2 3 8 1 superb q_q3 v-- 1 7 mirror q_q4 4 6 2 cascode q_q5 5 6 3 cascode r_r3 4 v++ 4.45e3 r_r4 5 v++ 4.45e3 c_c4 vin- 0 2e-12 c_c5 8 0 2e-12 d_d1 6 7 dx i_iee 1 v-- dc 200e-6 i_iee1 v++ 6 dc 96e-6 v_vos 9 in+ 5e-6 e_eos 8 9 vc vmid 1 * *1st gain stage g_g1 v++ 11 4 5 101.6828e-3 g_g2 v-- 11 4 5 101.6828e-3 r_r5 11 v++ 1 r_r6 v-- 11 1 d_d2 10 v++ dx d_d3 v-- 12 dx v_v1 10 11 1.86 v_v2 11 12 1.86 * *2nd gain stage g_g3 v++ vg 11 vmid 2.21e-3 g_g4 v-- vg 11 vmid 2.21e-3 r_r7 vg v++ 2.55e10 r_r8 v-- vg 2.55e10 c_c2 vg v++ 6.25e-10 c_c3 v-- vg 6.25e-10 d_d4 13 v++ dx d_d5 v-- 14 dx v_v3 13 vg 1.86 v_v4 vg 14 1.86 * *mid supply ref r_r9 vmid v++ 1 r_r10 v-- vmid 1 i_isy v+ v- dc 0.21e-3 e_e2 v++ 0 v+ 0 1 e_e3 v-- 0 v- 0 1 * *common mode gain stage with zero g_g5 v++ vc vcm vmid 5.62e-8 g_g6 v-- vc vcm vmid 5.62e-8 r_r11 vc 17 1 r_r12 18 vc 1 l_l1 17 v++ 1.59e-3 l_l2 18 v-- 1.59e-3 * *output stage with correction current sources g_g7 vout v++ v++ vg 1.11e-2 g_g8 v-- vout vg v-- 1.11e-2 g_g9 22 v-- vout vg 1.11e-2 g_g10 23 v-- vg vout 1.11e-2 d_d6 vg 20 dx d_d7 21 vg dx d_d8 v++ 22 dx d_d9 v++ 23 dx d_d10 v-- 22 dy d_d11 v-- 23 dy v_v5 20 vout 1.12 v_v6 vout 21 1.12 r_r15 vout v++ 9e1 r_r16 v-- vout 9e1 * .model superb npn + is=184e-15 bf=30e3 va=15 ik=70e-3 rb=50 + re=0.065 rc=35 cje=1.5e-12 cjc=2e-12 + kf=0 af=0 .model cascode npn + is=502e-18 bf=150 va=300 ik=17e-3 rb=140 + re=0.011 rc=900 cje=0.2e-12 cjc=0.16e-12f + kf=0 af=0 .model mirror pnp + is=4e-15 bf=150 va=50 ik=138e-3 rb=185 + re=0.101 rc=180 cje=1.34e-12 cjc=0.44e-12 + kf=0 af=0 .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28107subckt figure 55. spice net list isl28107, isl28207, isl28407 23 fn6631.3 september 9, 2010 characterization vs simulation results figure 56. characterized input noise voltage figure 57. simulated input noise voltage figure 58. characterized closed loop gain vs frequency figure 59. simulated cl osed loop gain vs frequency figure 60. characterized closed loop gain vs r l figure 61. simulated closed loop gain vs r l frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 0.1 1 10 100 1k 10k 100k v + = 19v a v = 1 frequency (hz) input noise voltage (nv/ hz) 100m 1.0 10 100 1k 10k 100k 10 100 1000 frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 -20 -10 0 10 20 30 40 50 60 70 a v = 1 a v = 100 a v = 1000 v + = 20v v out = 100mv p-p c l = 4pf r l = 10k a v = 10 r g = 1k, r f = 100k r g = 100, r f = 100k r g = open, r f = 0 r g = 10k, r f = 100k 10 100 10k 100k 1m 10m -20 0 20 40 70 60 frequency (hz) gain (db) a v = 1 a v = 100 a v = 1000 r g = 100, r f = 100k r g = 10k, r f = 100k a v = 10 r g = 1k, r f = 100k r g = open, r f = 0 1k normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 v + = 20v a v = +1 v out = 100mv p-p c l = 4pf r l = 10k r l = 100k r l = 1k r l = 499 1k 10k 100k 1m 10m -8 -6 -4 -2 0 -9 1 normalized gain (db) frequency (hz) v + = 15v a v = +1 v out = 100mv p-p c l = 4pf r l = 1k r l = 499 r l = 100k r l = 10k isl28107, isl28207, isl28407 24 fn6631.3 september 9, 2010 figure 62. characterized large signal 10v step response figure 63. simulated large signal 10v step response figure 64. simulated open-loop gain, phase vs frequency figure 65. simulated open-loop gain, phase vs frequency figure 66. simulated cmrr vs frequency characterization vs simulation results (continued) -6 -4 -2 0 2 4 6 0 50 100 150 200 250 300 350 400 time (s) large signal (v) v + = 15v a v = 11 c l = 4pf v out = 10v p-p r f = 10k, r g = 1k r l = 10k r l = 2k time (s) large signal (v) 0 50 100 150 200 250 300 -20 -10 0 10 20 output input open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 10pf gain phase 10m 1 100 10k 1m 100m 1m -50 0 50 100 150 200 open loop gain (db)/phase () frequency (hz) r l = 10k simulation c l = 10pf gain phase cmrr (db) frequency (hz) 1m 100m 10 1k 100k 10m 0 50 100 150 100m simulation isl28107, isl28207, isl28407 25 fn6631.3 september 9, 2010 revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 9/7/10 fn6631.3 1. general changes: a. added in isl28407 quad devices for soic, tssop and qfn packages. b. added in tdfn packages for single isl28107 and dual isl28207 devices. c. added in new vos and tcvos limits for tdfn packages 2. specific changes: a. on page 1 ? added in isl28407 to title and front pa ge info. corrected input bias current in features from 60pa to 15pa (in order to match spec table) b. on page 2 - added in isl28107frtz, isl28207 frtz, isl28407fbz, isl284 07fvz, and isl28407frz packages to ordering information. added in ?t7, t-13 & -t7a tape an d reel extensions where applicable. c. on page 2 -corrected part marking for isl28207frtz parts from 207z to 8207 d. on page 3 ? added in tdfn, 14 ld soic, 14 ld tssop and 16 ld qfn to pin configurations. e. on page 4 ? updated ?pin descri ptions? with newly added packages. f. on page 6 ? in ?thermal inform ation?, added in thermal packaging info & applicable notes for tdfn packages. g. on page 6 and page 8 electrical sp ecifications tables ? added two ne w line items for vos spec. tdfn package isl28107 limits 100uv 25c and 190uv full temp. tdfn package isl28207 limits 100uv 25c and 175uv full temp. h. on page 6 and page 8 electrical sp ecifications table ? added two new line items for tcvos spec. tdfn package isl28107 limits 0.9uv/c full temp. tdfn package isl28207 limits 0.75uv/c. i. on page 28 to page 32 - added in pod for l8.3x3a, m14.15, m14.173, and l16.4x4 3/9/10 fn6631.2 1. added msop package to the ordering inform ation and added applicable pod m8.118 to end of datasheet 2. separated each part number with it's ow n specific -t7 and -t13 suffix. removed ?add ?-t7? or ?-t13? suffix for tape and reel.? from note 1. 3. added msop to the pin configuration and pin descriptions 4. updated 15 and 5v electrical spec ification table with the following edits: a) separated vos specs for soic and msop packages. added ne w vos specs for msop grade package. b) separated tcvos specs for soic and msop packages. added new tcvos specs for msop package. 5. added theta ja and jc for the 8 ld msop packag e. added theta jc values for both soic package options. changed theta ja for 8 ld soic (isl28207) from 115 to 105. 2/22/10 1. added ?related lite rature*(see page 26)? on page 1. 2. added evaluation boards to ?ordering information? on page 2. 3. ?electrical specifications? tables, page 6 to page 9. unbolded min/max specs with ?t a = -40c to +85c? conditions (since only min/max specs with ?t a = -40c to +125c? conditions should be bolded, per note in common conditions) 4. corrected note reference in i sc parameter on page 7 and page 9 from note 3 to note 9. 11/10/09 fn6631.1 1. updated vos, ib, and ios electrical specifications. 2. added typical performance curves, figures 1 through 30. 3. output short circuit current test co ndition has been clarified with note 9. 4. updated pod. 5. added spice model, associated text and figures 56 through 66. 6. deleted old figures 6, 7, 8, 10, 11 and 12. 7. added licence statement on page 16 and referenced in spice model. 6/5/09 fn6631.0 initial release. isl28107, isl28207, isl28407 26 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6631.3 september 9, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl28107 , isl28207 and isl28407. to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php isl28107, isl28207, isl28407 27 fn6631.3 september 9, 2010 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b? isl28107, isl28207, isl28407 28 fn6631.3 september 9, 2010 isl28107, isl28207, isl28407 package outline drawing m8.118 8 lead mini small outline plastic package rev 3, 3/10 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.036 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m 29 fn6631.3 september 9, 2010 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7. isl28107, isl28207, isl28407 30 fn6631.3 september 9, 2010 package outline drawing m14.15 14 lead narrow body small outline plastic package rev 1, 10/09 a d 4 0.25 a-b mc c 0.10 c 5 b d 3 0.10 a-b c 4 0.20 c 2x 2x 0.10 d c 2x h 0.10 c 6 3 6 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 1.27 0.31-0.51 4 4 detail"a" 0.220.03 0.10-0.25 1.25 min 1.75 max (1.27) (0.6) 6.0 8.65 3.9 7 14 8 dimensioning and tolerancing conform to amsey14.5m-1994. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. interlead flash or protrusions shall not exceed 0.25mm per side. datums a and b to be determined at datum h. 4. 5. 3. 2. dimensions are in millimeters. notes: 1. the pin #1 indentifier may be either a mold or mark feature. 6. does not include dambar protrusion. allowable dambar protrusion 7. reference to jedec ms-012-ab. shall be 0.10mm total in excess of lead width at maximum condition. detail "a" side view typical recommended land pattern top view isl28107, isl28207, isl28407 31 fn6631.3 september 9, 2010 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view isl28107, isl28207, isl28407 32 fn6631.3 september 9, 2010 package outline drawing l16.4x4 16 lead quad flat no-lead plastic package rev 6, 02/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view index area (4x) 0.15 pin 1 6 4.00 4.00 a b +0.15 -0.10 16x 0 . 60 2 . 10 0 . 15 0.28 +0.07 / -0.05 pin #1 index area 5 8 4 0.10 c m 12 9 4 0.65 12x 13 4x 1.95 16 1 6 a b ( 3 . 6 typ ) ( 2 . 10 ) ( 12x 0 . 65 ) ( 16x 0 . 28 ) ( 16 x 0 . 8 ) see detail "x" base plane 1.00 max 0 . 2 ref 0 . 00 min. 0 . 05 max. c 5 0.08 c c seating plane 0.10 c isl28107, isl28207, isl28407 |
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